1. Field of the Invention
The present invention relates to frame buffer memory systems for raster displays, and more particularly to a frame buffer memory controller for allowing rapid picture updating while maintaining screen refresh data flow rate.
2. Description of the Prior Art
Raster scan, frame buffer displays have become increasingly popular as the price of semiconductor memory has decreased. The image to be displayed is represented in a large memory that saves a digital representation of the intensity and/or color of each picture element, or pixel, on the screen. By properly recording the data in the memory an arbitrary image can be displayed, making the display hardware insensitive to image content. The frame buffer memory is equipped with hardware to generate a video signal to refresh the display and with a memory port to allow a host computer or display processor to change the frame buffer memory in order to change the image being displayed.
Interactive graphics applications require rapid changes to the displayed image, which in turn require rapid changes to the frame buffer memory. Although the speed of the host processor and display processor is clearly important to high performance, so also are the properties of the memory system, such as update bandwidth, i.e., the rate at which the host processor or data processor may access each pixel. For a given memory technology the implicit geometry of frame buffer memory access can affect this rate. Conventional pixel memory systems arrange words of memory so that a single memory cycle provides access to sixteen, twenty, thirty-two, or some other fixed number of pixels in a horizontal scan line on a display. Other systems use arrays of pixels, such as 4.times.4, 4.times.5, 8.times.8, etc. for each frame buffer word.
A conventional frame buffer memory writes pixels along a horizontal line very rapidly, but is slow for most other directions. For a frame buffer memory with a 16 pixel wide by 1 pixel high word, let the average time to do a memory write be T seconds (including the delay caused by interspersed display refresh reads). Then horizontal lines can be written at a rate as high as 16/T pixels per second. Since the beginning and end of the lines will generally not lie on word boundaries, the actual rate will be less than 16/T on average. Now consider a vertical line, or any line steeper than 45 degrees. Every pixel written will lie in a different word. The pixel rate is thus 1/T pixels per second. Averaging the pixel drawing rate over all vector angles and ignoring the end effects gives roughly 1.36/T pixels per second. Frame buffer memories with words covering a rectangular array of pixels improve on the average pixel writing rate. For a frame buffer memory with a 4 pixel wide by 4 pixel high word and average writing time T, except for the beginning and end of lines, 4 pixels can be written on each memory cycle independent of the orientation of the line. The pixel writing rate thus approaches 4/T pixels per second.
What is desired is a means for speeding up the process of updating the image in frame buffer memory, i.e., increasing update bandwidth.